1. Field of the Invention
Embodiments of the invention relate to the field of device manufacturing. More particularly, the present invention relates to a method, system and structure for forming a multi-gate transistor.
2. Discussion of Related Art
As semiconductor devices including logic devices based on complementary-metal-oxide-semiconductor (CMOS) architecture continue to scale to smaller dimensions, a transition between conventional planar devices to non-planar devices is taking place in order to preserve the ability to scale performance and device density in keeping with historical trends described by Moore's law. In particular, three-dimensional multigate structures, such as the so-called Fin-type field effect transistor, or FinFET, are under active development to replace planar CMOS devices for coming technology generations.
The term FinFET was coined by University of California, Berkeley researchers to describe a nonplanar, double-gate transistor. A distinguishing characteristic of the FinFET is that the conducting channel is formed by a silicon-based “fin” that extends orthogonally from the surface of a substrate and is wrapped by a gate such that the channel can be gated from opposite sides. The electrical field applied by the gate on opposite sides of the fin extends generally parallel to the surface of the FinFET substrate, as opposed to conventional planar CMOS devices in which the transistor gate produces a field generally orthogonal to the plane of the CMOS substrate. Other, related multigate devices, such as the so-called tri-gate technology, also employ fin-type structures to form conducting channels that are gated upon multiple sides.
In typical FinFET fabrication, before channel structures (that is, fins) are formed, implantation of heavy ion species is performed to control dopant placement and diffusion, such as an isolation/ground plane implantation process. This implantation step is typically performed using species such as As, Sb, P, BF2, Ga or In, among others, and is used to prevent degradation in device resistivity and/or leakage. However, as a consequence of implantation, heavy crystalline damage may be imparted into the substrate, such that the single-crystal silicon structure in the substrate cannot be fully recovered in subsequent thermal processing. Consequently, when fin-type structures are subsequently fabricated, the defect levels in the fins and/or adjacent silicon substrate may be excessive. This results in degraded device characteristics caused by dissipative phenomena arising from residual crystalline damage, including increased resistance and device leakage. In addition, variability in device performance may be increased by the residual defects from the implantation. This may also lead to a decrease in process window for producing devices having acceptable characteristics. In view of the above, it will be appreciated that there is a need for an improved multigate CMOS processes and device structures.